With the evolving of semiconductor technologies, semiconductor dies are becoming increasingly smaller and thinner. As a result, semiconductor packages are becoming more compact.
Package technologies can be divided into two categories. One category of packaging is referred to as chip-level packaging, in which dies are sawed from wafers before they are packaged. Advantageously, only “known-good-dies” are packaged. Another advantageous feature of this packaging technology is the possibility of forming fan-out chip packages, which means that the I/O pads on a die can be redistributed to a greater area than the die, and hence the number of I/O pads packed on the surfaces of the dies can be increased.
After dies are bonded to a wafer, the resulting structure, including the dies and the wafer, have an uneven surface due to the height of the dies and the gaps between the dies. This results in process difficulty in subsequent process steps, such as die sawing. Further, the wafer may be thin, and hence with the uneven surface and possible relative great thickness of the dies, the wafer is prone to breakage.
Molding compounds may be filled between the gaps of dies to planarize the surface of the resulting packaging structure. However, molding compounds typically have low thermal conductivities, and the resulting three-dimensional integrated circuits (3DICs) also have a low heat-dissipating capability. In addition, with the more compact 3DICs, more heat is generated in the 3DIC, making the heat dissipation a serious issue.